Perf improve for Intel MTL CPUs #19379
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Let's not merge this to main. We'll give a nightly build to Intel from this branch to verify and then discuss with them today about next steps. |
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Because I cannot verify the code change on the hardware our team has, I am waiting feedback from Intel. |
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I will create a new PR if Intel told me the change was good. |
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Description
This PR copies the code that was added in #18384 to the core framework.
AB#22668
Motivation and Context
Intel's latest mobile platform CPU added a new type CPU cores: SoC cores. The SoC cores are very low performance, but highly power efficient. By default when ONNX Runtime creates a thread pool, it creates one thread for each CPU core. I was told by an Intel engineer that if we exclude the SoC core from computing the number of threads, ONNX Runtime's performance will be significantly improved. Hence this change was made. The two files hardware_core_enumerator.h and hardware_core_enumerator.cc were not written by me. They are the major part of this change. The code in the two files tries to detect if a CPU core is a SoC core in an indirect way: supposedly every Intel CPU should have three levels of cache, if a core only has two levels of cache, it must be a SoC core.